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[PWGEM/Dilepton] reduce muon table size (#15201)
Co-authored-by: ALICE Action Bot <alibuild@cern.ch>
1 parent 13b0a7e commit f785f4e

19 files changed

+344
-216
lines changed

‎PWGEM/Dilepton/Core/Dilepton.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ struct Dilepton {
186186
Configurable<float> cfg_min_dphi{"cfg_min_dphi", 0.2, "min dphi between 2 electrons (elliptic cut)"};
187187
Configurable<float> cfg_min_opang{"cfg_min_opang", 0.0, "min opening angle"};
188188
Configurable<float> cfg_max_opang{"cfg_max_opang", 6.4, "max opening angle"};
189-
Configurable<bool> cfg_require_diff_sides{"cfg_require_diff_sides", false, "flag to require 2 tracks are from different sides."};
189+
// Configurable<bool> cfg_require_diff_sides{"cfg_require_diff_sides", false, "flag to require 2 tracks are from different sides."};
190190

191191
Configurable<bool> cfg_apply_cuts_from_prefilter{"cfg_apply_cuts_from_prefilter", false, "flag to apply prefilter set when producing derived data"};
192192
Configurable<uint16_t> cfg_prefilter_bits{"cfg_prefilter_bits", 0, "prefilter bits [kNone : 0, kElFromPC : 1, kElFromPi0_20MeV : 2, kElFromPi0_40MeV : 4, kElFromPi0_60MeV : 8, kElFromPi0_80MeV : 16, kElFromPi0_100MeV : 32, kElFromPi0_120MeV : 64, kElFromPi0_140MeV : 128] Please consider logical-OR among them."}; // see PairUtilities.h
@@ -215,8 +215,8 @@ struct Dilepton {
215215
Configurable<bool> cfg_require_itsib_1st{"cfg_require_itsib_1st", true, "flag to require ITS ib 1st hit"};
216216
Configurable<float> cfg_min_its_cluster_size{"cfg_min_its_cluster_size", 0.f, "min ITS cluster size"};
217217
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
218-
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
219-
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};
218+
// Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
219+
// Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};
220220
Configurable<float> cfgRefR{"cfgRefR", 0.50, "ref. radius (m) for calculating phi position"}; // 0.50 +/- 0.06 can be syst. unc.
221221
Configurable<float> cfg_min_phiposition_track{"cfg_min_phiposition_track", 0.f, "min phi position for single track at certain radius"};
222222
Configurable<float> cfg_max_phiposition_track{"cfg_max_phiposition_track", 6.3, "max phi position for single track at certain radius"};
@@ -708,7 +708,7 @@ struct Dilepton {
708708
fDielectronCut.ApplyPhiV(dielectroncuts.cfg_apply_phiv);
709709
fDielectronCut.SetMindEtadPhi(dielectroncuts.cfg_apply_detadphi, false, dielectroncuts.cfg_min_deta, dielectroncuts.cfg_min_dphi);
710710
fDielectronCut.SetPairOpAng(dielectroncuts.cfg_min_opang, dielectroncuts.cfg_max_opang);
711-
fDielectronCut.SetRequireDifferentSides(dielectroncuts.cfg_require_diff_sides);
711+
// fDielectronCut.SetRequireDifferentSides(dielectroncuts.cfg_require_diff_sides);
712712

713713
// for track
714714
fDielectronCut.SetTrackPtRange(dielectroncuts.cfg_min_pt_track, dielectroncuts.cfg_max_pt_track);
@@ -727,7 +727,7 @@ struct Dilepton {
727727
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
728728
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
729729
fDielectronCut.SetChi2TOF(0, dielectroncuts.cfg_max_chi2tof);
730-
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);
730+
// fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);
731731

732732
// for eID
733733
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
@@ -1111,19 +1111,19 @@ struct Dilepton {
11111111
used_trackIds_per_col.emplace_back(t1.globalIndex());
11121112
if (cfgDoMix) {
11131113
if (t1.sign() > 0) {
1114-
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXXatDCA(), t1.cXYatDCA(), t1.cYYatDCA()));
1114+
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXX(), t1.cXY(), t1.cYY()));
11151115
} else {
1116-
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXXatDCA(), t1.cXYatDCA(), t1.cYYatDCA()));
1116+
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXX(), t1.cXY(), t1.cYY()));
11171117
}
11181118
}
11191119
}
11201120
if (std::find(used_trackIds_per_col.begin(), used_trackIds_per_col.end(), t2.globalIndex()) == used_trackIds_per_col.end()) {
11211121
used_trackIds_per_col.emplace_back(t2.globalIndex());
11221122
if (cfgDoMix) {
11231123
if (t2.sign() > 0) {
1124-
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXXatDCA(), t2.cXYatDCA(), t2.cYYatDCA()));
1124+
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXX(), t2.cXY(), t2.cYY()));
11251125
} else {
1126-
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXXatDCA(), t2.cXYatDCA(), t2.cYYatDCA()));
1126+
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXX(), t2.cXY(), t2.cYY()));
11271127
}
11281128
}
11291129
}

‎PWGEM/Dilepton/Core/DileptonHadronMPC.h‎

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@ struct DileptonHadronMPC {
208208
Configurable<float> cfg_max_dcaz{"cfg_max_dcaz", 1.0, "max dca Z for single track in cm"};
209209
Configurable<bool> cfg_require_itsib_any{"cfg_require_itsib_any", false, "flag to require ITS ib any hits"};
210210
Configurable<bool> cfg_require_itsib_1st{"cfg_require_itsib_1st", true, "flag to require ITS ib 1st hit"};
211-
Configurable<float> cfgRefR{"cfgRefR", 1.2, "reference R (in m) for extrapolation"}; // https://cds.cern.ch/record/1419204
211+
Configurable<float> cfgRefR{"cfgRefR", 0.5, "reference R (in m) for extrapolation"}; // https://cds.cern.ch/record/1419204
212212

213213
Configurable<int> cfg_pid_scheme{"cfg_pid_scheme", static_cast<int>(DielectronCut::PIDSchemes::kTPChadrejORTOFreq), "pid scheme [kTOFreq : 0, kTPChadrej : 1, kTPChadrejORTOFreq : 2, kTPConly : 3, kTOFif : 4, kPIDML : 5, kTPChadrejORTOFreq_woTOFif : 6]"};
214214
Configurable<float> cfg_min_TPCNsigmaEl{"cfg_min_TPCNsigmaEl", -2.0, "min. TPC n sigma for electron inclusion"};
@@ -617,7 +617,6 @@ struct DileptonHadronMPC {
617617
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
618618
fDielectronCut.SetChi2TOF(0, dielectroncuts.cfg_max_chi2tof);
619619
fDielectronCut.SetRelDiffPin(-1e+10, +1e+10);
620-
fDielectronCut.IncludeITSsa(false, 0.15);
621620

622621
// for eID
623622
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);
@@ -807,19 +806,19 @@ struct DileptonHadronMPC {
807806
used_trackIds_per_col.emplace_back(t1.globalIndex());
808807
if (cfgDoMix) {
809808
if (t1.sign() > 0) {
810-
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXXatDCA(), t1.cXYatDCA(), t1.cYYatDCA()));
809+
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXX(), t1.cXY(), t1.cYY()));
811810
} else {
812-
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXXatDCA(), t1.cXYatDCA(), t1.cYYatDCA()));
811+
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t1.pt(), t1.eta(), t1.phi(), leptonM1, t1.sign(), t1.fwdDcaX(), t1.fwdDcaY(), t1.cXX(), t1.cXY(), t1.cYY()));
813812
}
814813
}
815814
}
816815
if (std::find(used_trackIds_per_col.begin(), used_trackIds_per_col.end(), t2.globalIndex()) == used_trackIds_per_col.end()) {
817816
used_trackIds_per_col.emplace_back(t2.globalIndex());
818817
if (cfgDoMix) {
819818
if (t2.sign() > 0) {
820-
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXXatDCA(), t2.cXYatDCA(), t2.cYYatDCA()));
819+
emh_pos->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXX(), t2.cXY(), t2.cYY()));
821820
} else {
822-
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXXatDCA(), t2.cXYatDCA(), t2.cYYatDCA()));
821+
emh_neg->AddTrackToEventPool(key_df_collision, EMFwdTrack(t2.pt(), t2.eta(), t2.phi(), leptonM2, t2.sign(), t2.fwdDcaX(), t2.fwdDcaY(), t2.cXX(), t2.cXY(), t2.cYY()));
823822
}
824823
}
825824
}
@@ -844,9 +843,9 @@ struct DileptonHadronMPC {
844843
return false;
845844
}
846845
}
847-
if (t1.trackId() == t3.trackId() || t2.trackId() == t3.trackId()) {
848-
return false;
849-
}
846+
// if (t1.trackId() == t3.trackId() || t2.trackId() == t3.trackId()) {
847+
// return false;
848+
// }
850849
} else if constexpr (pairtype == o2::aod::pwgem::dilepton::utils::pairutil::DileptonPairType::kDimuon) {
851850
if (!cut.template IsSelectedTrack<false>(t1) || !cut.template IsSelectedTrack<false>(t2)) {
852851
return false;
@@ -947,9 +946,9 @@ struct DileptonHadronMPC {
947946
continue;
948947
}
949948
}
950-
if (t1.trackId() == pos.trackId() || t2.trackId() == pos.trackId()) {
951-
return false;
952-
}
949+
// if (t1.trackId() == pos.trackId() || t2.trackId() == pos.trackId()) {
950+
// return false;
951+
// }
953952
} // end of pos lepton loop
954953

955954
for (const auto& neg : negLeptons) { // leptons per collision
@@ -962,9 +961,9 @@ struct DileptonHadronMPC {
962961
continue;
963962
}
964963
}
965-
if (t1.trackId() == neg.trackId() || t2.trackId() == neg.trackId()) {
966-
return false;
967-
}
964+
// if (t1.trackId() == neg.trackId() || t2.trackId() == neg.trackId()) {
965+
// return false;
966+
// }
968967
} // end of neg lepton lopp
969968

970969
} // end of if kDielectron

‎PWGEM/Dilepton/Core/DileptonMC.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,7 @@ struct DileptonMC {
188188
Configurable<float> cfg_min_dphi{"cfg_min_dphi", 0.2, "min dphi between 2 electrons (elliptic cut)"};
189189
Configurable<float> cfg_min_opang{"cfg_min_opang", 0.0, "min opening angle"};
190190
Configurable<float> cfg_max_opang{"cfg_max_opang", 6.4, "max opening angle"};
191-
Configurable<bool> cfg_require_diff_sides{"cfg_require_diff_sides", false, "flag to require 2 tracks are from different sides."};
191+
// Configurable<bool> cfg_require_diff_sides{"cfg_require_diff_sides", false, "flag to require 2 tracks are from different sides."};
192192

193193
Configurable<bool> cfg_apply_cuts_from_prefilter{"cfg_apply_cuts_from_prefilter", false, "flag to apply prefilter set when producing derived data"};
194194
Configurable<uint16_t> cfg_prefilter_bits{"cfg_prefilter_bits", 0, "prefilter bits [kNone : 0, kElFromPC : 1, kElFromPi0_20MeV : 2, kElFromPi0_40MeV : 4, kElFromPi0_60MeV : 8, kElFromPi0_80MeV : 16, kElFromPi0_100MeV : 32, kElFromPi0_120MeV : 64, kElFromPi0_140MeV : 128] Please consider logical-OR among them."}; // see PairUtilities.h
@@ -217,8 +217,8 @@ struct DileptonMC {
217217
Configurable<bool> cfg_require_itsib_1st{"cfg_require_itsib_1st", true, "flag to require ITS ib 1st hit"};
218218
Configurable<float> cfg_min_its_cluster_size{"cfg_min_its_cluster_size", 0.f, "min ITS cluster size"};
219219
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
220-
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
221-
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};
220+
// Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
221+
// Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};
222222
Configurable<float> cfgRefR{"cfgRefR", 0.50, "ref. radius (m) for calculating phi position"}; // 0.50 +/- 0.06 can be syst. unc.
223223
Configurable<float> cfg_min_phiposition_track{"cfg_min_phiposition_track", 0.f, "min phi position for single track at certain radius"};
224224
Configurable<float> cfg_max_phiposition_track{"cfg_max_phiposition_track", 6.3, "max phi position for single track at certain radius"};
@@ -715,7 +715,7 @@ struct DileptonMC {
715715
fDielectronCut.ApplyPhiV(dielectroncuts.cfg_apply_phiv);
716716
fDielectronCut.SetMindEtadPhi(dielectroncuts.cfg_apply_detadphi, false, dielectroncuts.cfg_min_deta, dielectroncuts.cfg_min_dphi);
717717
fDielectronCut.SetPairOpAng(dielectroncuts.cfg_min_opang, dielectroncuts.cfg_max_opang);
718-
fDielectronCut.SetRequireDifferentSides(dielectroncuts.cfg_require_diff_sides);
718+
// fDielectronCut.SetRequireDifferentSides(dielectroncuts.cfg_require_diff_sides);
719719

720720
// for track
721721
fDielectronCut.SetTrackPtRange(dielectroncuts.cfg_min_pt_track, dielectroncuts.cfg_max_pt_track);
@@ -734,7 +734,7 @@ struct DileptonMC {
734734
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
735735
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
736736
fDielectronCut.SetChi2TOF(0.0, dielectroncuts.cfg_max_chi2tof);
737-
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);
737+
// fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);
738738

739739
// for eID
740740
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);

‎PWGEM/Dilepton/Core/DileptonProducer.h‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ struct DileptonProducer {
162162
Configurable<float> cfg_min_dphi{"cfg_min_dphi", 0.2, "min dphi between 2 electrons (elliptic cut)"};
163163
Configurable<float> cfg_min_opang{"cfg_min_opang", 0.0, "min opening angle"};
164164
Configurable<float> cfg_max_opang{"cfg_max_opang", 6.4, "max opening angle"};
165-
Configurable<bool> cfg_require_diff_sides{"cfg_require_diff_sides", false, "flag to require 2 tracks are from different sides."};
165+
// Configurable<bool> cfg_require_diff_sides{"cfg_require_diff_sides", false, "flag to require 2 tracks are from different sides."};
166166

167167
Configurable<bool> cfg_apply_cuts_from_prefilter{"cfg_apply_cuts_from_prefilter", false, "flag to apply prefilter set when producing derived data"};
168168
Configurable<uint16_t> cfg_prefilter_bits{"cfg_prefilter_bits", 0, "prefilter bits [kNone : 0, kElFromPC : 1, kElFromPi0_20MeV : 2, kElFromPi0_40MeV : 4, kElFromPi0_60MeV : 8, kElFromPi0_80MeV : 16, kElFromPi0_100MeV : 32, kElFromPi0_120MeV : 64, kElFromPi0_140MeV : 128] Please consider logical-OR among them."}; // see PairUtilities.h
@@ -191,8 +191,8 @@ struct DileptonProducer {
191191
Configurable<bool> cfg_require_itsib_1st{"cfg_require_itsib_1st", true, "flag to require ITS ib 1st hit"};
192192
Configurable<float> cfg_min_its_cluster_size{"cfg_min_its_cluster_size", 0.f, "min ITS cluster size"};
193193
Configurable<float> cfg_max_its_cluster_size{"cfg_max_its_cluster_size", 16.f, "max ITS cluster size"};
194-
Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
195-
Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};
194+
// Configurable<float> cfg_min_rel_diff_pin{"cfg_min_rel_diff_pin", -1e+10, "min rel. diff. between pin and ppv"};
195+
// Configurable<float> cfg_max_rel_diff_pin{"cfg_max_rel_diff_pin", +1e+10, "max rel. diff. between pin and ppv"};
196196
Configurable<float> cfgRefR{"cfgRefR", 0.50, "ref. radius (m) for calculating phi position"}; // 0.50 +/- 0.06 can be syst. unc.
197197
Configurable<float> cfg_min_phiposition_track{"cfg_min_phiposition_track", 0.f, "min phi position for single track at certain radius"};
198198
Configurable<float> cfg_max_phiposition_track{"cfg_max_phiposition_track", 6.3, "max phi position for single track at certain radius"};
@@ -213,8 +213,6 @@ struct DileptonProducer {
213213
Configurable<float> cfg_min_pin_pirejTPC{"cfg_min_pin_pirejTPC", 0.f, "min. pin for pion rejection in TPC"};
214214
Configurable<float> cfg_max_pin_pirejTPC{"cfg_max_pin_pirejTPC", 1e+10, "max. pin for pion rejection in TPC"};
215215
Configurable<bool> enableTTCA{"enableTTCA", true, "Flag to enable or disable TTCA"};
216-
Configurable<bool> includeITSsa{"includeITSsa", false, "Flag to enable ITSsa tracks"};
217-
Configurable<float> cfg_max_pt_track_ITSsa{"cfg_max_pt_track_ITSsa", 0.15, "max pt for ITSsa tracks"};
218216

219217
// configuration for PID ML
220218
Configurable<std::vector<std::string>> onnxFileNames{"onnxFileNames", std::vector<std::string>{"filename"}, "ONNX file names for each bin (if not from CCDB full path)"};
@@ -393,7 +391,7 @@ struct DileptonProducer {
393391
fDielectronCut.ApplyPhiV(dielectroncuts.cfg_apply_phiv);
394392
fDielectronCut.SetMindEtadPhi(dielectroncuts.cfg_apply_detadphi, false, dielectroncuts.cfg_min_deta, dielectroncuts.cfg_min_dphi);
395393
fDielectronCut.SetPairOpAng(dielectroncuts.cfg_min_opang, dielectroncuts.cfg_max_opang);
396-
fDielectronCut.SetRequireDifferentSides(dielectroncuts.cfg_require_diff_sides);
394+
// fDielectronCut.SetRequireDifferentSides(dielectroncuts.cfg_require_diff_sides);
397395

398396
// for track
399397
fDielectronCut.SetTrackPtRange(dielectroncuts.cfg_min_pt_track, dielectroncuts.cfg_max_pt_track);
@@ -412,8 +410,7 @@ struct DileptonProducer {
412410
fDielectronCut.RequireITSibAny(dielectroncuts.cfg_require_itsib_any);
413411
fDielectronCut.RequireITSib1st(dielectroncuts.cfg_require_itsib_1st);
414412
fDielectronCut.SetChi2TOF(0, dielectroncuts.cfg_max_chi2tof);
415-
fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);
416-
fDielectronCut.IncludeITSsa(dielectroncuts.includeITSsa, dielectroncuts.cfg_max_pt_track_ITSsa);
413+
// fDielectronCut.SetRelDiffPin(dielectroncuts.cfg_min_rel_diff_pin, dielectroncuts.cfg_max_rel_diff_pin);
417414

418415
// for eID
419416
fDielectronCut.SetPIDScheme(dielectroncuts.cfg_pid_scheme);

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