diff --git a/docs/Targets.md b/docs/Targets.md index 0bfa40e4dd..2c07dcb1f4 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -2749,6 +2749,10 @@ section, e.g.: If an external `.dcd_data` section is provided, the option `NXP_CUSTOM_DCD=1` must be added to the configuration. +### FlexSPI Configuration Block (FCB) Look-Up Table (LUT) + +By default the read LUT sequence for all i.MX RT targets uses a quad read. If your flash chip does not support this feature by default, e.g. the QE-bit is disabled from the factory, it is necessary to use a single read instead. This can be accomplished by defining `CONFIG_IMX_FCB_LUT_SINGLE_READ_DATA` when compiling wolfBoot, e.g. by adding it to the `CFLAGS_EXTRA` variable in the configuration file. + ### Building wolfBoot for HAB (High Assurance Boot) The `imx_rt` target supports building without a flash configuration, IVT, Boot Data and DCD. This is needed when wanting to use HAB through NXP's *Secure Provisioning Tool* to sign wolfBoot to enable secure boot. To build wolfBoot this way `TARGET_IMX_HAB` needs to be set to 1 in the configuration file (see `config/examples/imx-rt1060 _hab.config` for an example). When built with `TARGET_IMX_HAB=1` wolfBoot must be written to flash using NXP's *Secure Provisioning Tool*. diff --git a/hal/imx_rt.c b/hal/imx_rt.c index f1eca55459..e98ecc296c 100644 --- a/hal/imx_rt.c +++ b/hal/imx_rt.c @@ -280,8 +280,13 @@ const flexspi_nor_config_t FLASH_CONFIG_SECTION qspiflash_config = { .serialClkFreq = CONFIG_SERIAL_CLK_FREQ, .sflashA1Size = CONFIG_FLASH_SIZE, .lookupTable = { +#if defined(CONFIG_IMX_FCB_LUT_SINGLE_READ_DATA) + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x03, RADDR_SDR, FLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0), +#else /* Default assumes flash chip supports Fast Read Quad (command 0xEB) out-of-the-box (has QE-bit enabled) */ FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), +#endif }, }, .pageSize = CONFIG_FLASH_PAGE_SIZE, @@ -340,8 +345,13 @@ const flexspi_nor_config_t FLASH_CONFIG_SECTION qspiflash_config = { .serialClkFreq = CONFIG_SERIAL_CLK_FREQ, .sflashA1Size = CONFIG_FLASH_SIZE, .lookupTable = { +#if defined(CONFIG_IMX_FCB_LUT_SINGLE_READ_DATA) + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x03, RADDR_SDR, FLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0), +#else /* Default assumes flash chip supports Fast Read Quad (command 0xEB) out-of-the-box (has QE-bit enabled) */ FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), +#endif }, }, .pageSize = CONFIG_FLASH_PAGE_SIZE, @@ -581,6 +591,10 @@ const flexspi_nor_config_t FLASH_CONFIG_SECTION qspiflash_config = { READ_SDR, FLEXSPI_4PAD, 0x04 /* any non-zero value */, JMP_ON_CS, FLEXSPI_1PAD, 0x01), #else + #if defined(CONFIG_IMX_FCB_LUT_SINGLE_READ_DATA) + [LUT_SEQ_IDX_0 + LUT_SEQ_INS_0_1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x03, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [LUT_SEQ_IDX_0 + LUT_SEQ_INS_2_3] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0), + #else /* Default assumes flash chip supports Fast Read Quad (command 0xEB) out-of-the-box (has QE-bit enabled) */ /* Quad Input/output read sequence */ [LUT_SEQ_IDX_0 + LUT_SEQ_INS_0_1] = FLEXSPI_LUT_SEQ( CMD_SDR, FLEXSPI_1PAD, 0xEB, @@ -588,6 +602,7 @@ const flexspi_nor_config_t FLASH_CONFIG_SECTION qspiflash_config = { [LUT_SEQ_IDX_0 + LUT_SEQ_INS_2_3] = FLEXSPI_LUT_SEQ( DUMMY_SDR, FLEXSPI_4PAD, 0x06 /* 6 dummy cycles */, READ_SDR, FLEXSPI_4PAD, 0x04 /* any non-zero value */ ), + #endif #endif /* Read Status */ [LUT_SEQ_IDX_1 + LUT_SEQ_INS_0_1] = FLEXSPI_LUT_SEQ(